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[VHDL-FPGA-Verilog] UARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] cascaded_adder

Description: implementation of cascade adder with verilog plus testbench
Platform: | Size: 4096 | Author: shabnam | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] asynfifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
Platform: | Size: 25600 | Author: iechshy1985 | Hits:

[Other] alu

Description: ALU modeling verilog codes and testbench
Platform: | Size: 545792 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

[VHDL-FPGA-Verilog] Springer_2006_SystemVerilog_for_Verificatio_Chris

Description: A Guide to Learning the Testbench System Verilog Language Features
Platform: | Size: 1412096 | Author: aj000 | Hits:

[VHDL-FPGA-Verilog] Writing_Testbenches_using_System_Verilog

Description: Testbench creation and development methodology with System Verilog. By Janick Bergeron.
Platform: | Size: 2764800 | Author: aj000 | Hits:

[VHDL-FPGA-Verilog] fifo_32_4321

Description: 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench-Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
Platform: | Size: 5120 | Author: keven | Hits:

[Other] HDL_CHIP_DESIGN[1]

Description: 介绍了如何编写正确且有效的vhdl/verilog hdl testbench,详细讲解了仿真测试程序的编写-Describes how to write correct and effective vhdl/verilog hdl testbench, explained in detail the preparation of the simulation test procedure
Platform: | Size: 5524480 | Author: neo | Hits:

[Other] howtowritetestbench

Description: verilog 怎样写 testbench，很有用-teach you how to write a testbench in verilog
Platform: | Size: 196608 | Author: ponny213 | Hits:

[VHDL-FPGA-Verilog] VERILOG-jpeg

Description: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Platform: | Size: 103424 | Author: ken | Hits:

[Documents] Lecture_Verification

Description: Writing testbench in verilog
Platform: | Size: 387072 | Author: gharib | Hits:

[Software Engineering] Stepper_controller_MAx

Description: stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable
Platform: | Size: 76800 | Author: pravin | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
Platform: | Size: 64512 | Author: Yang Jie | Hits:

[VHDL-FPGA-Verilog] verilog_testbench_genetator

Description: 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as aaa.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------|
Platform: | Size: 2048 | Author: zishan | Hits:

[VHDL-FPGA-Verilog] testbench(vhdl)

Description: 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
Platform: | Size: 36864 | Author: xy | Hits:

[VHDL-FPGA-Verilog] FifoAndTestbench

Description: 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
Platform: | Size: 2048 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] fifo_tb

Description: verilog implementation of 16X4 fifo with testbench
Platform: | Size: 1024 | Author: prateek | Hits:

[VHDL-FPGA-Verilog] verilog-testbench-preliminary

Description: 本文简单介绍了逻辑验证的入门知识—如何编写TESTBENCH进行逻辑测试-This paper briefly introduces the logic verification started- how to write TESTBENCH logic test
Platform: | Size: 61440 | Author: zx | Hits:
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